QL82SD Device Data Sheet
****** Device Highlights
LVDS SERDES Basic Features
* 10 High Speed Bus LVDS Serial Links-- *
Extended Features
The following can be implemented into the programmable logic:
* UTOPIA Level 2, 16-bit wide System
*
*
* * * * * * * * * * * * * *
bandwidth up to 5 Gbps Eight Independent Bus LVDS serial transceivers with operating speeds to 632 Mbps per channel Two Independent Bus LVDS clock serial transceivers with operating speeds to 400 MHz per channel Integrated clock and data recovery (CDR) with no external analog components required CDR bypass for applications with external clock source Programmable serial to parallel configuration 10-bit data width--with clock recovery 4-bit, 7-bit and 8-bit data widths-- with external clock 1-bit asynchronous level conversion Fast Lock and Random (auto) Lock capable Lock signal feedback I/O support for LVTTL, LVCMOS, PCI, GTL+, SSTL2, SSTL3, LVDS, LVPECL Low Power/Independent power-down mode for each SERDES channel IEEE1149.1 JTAG Support & boundary scan Operation over PCB or backplane traces, or across twisted pair cabling up to 25 m Point-to-Point, Multi-Point, and Multi-Drop Support Pre-Emphasis Control on each LVDS Channel Link
*
* *
*
interface (up to 50 MHz) with parity support for ATM applications UTOPIA Level 3 compatible 8-bit wide system Interface (up to 100 MHz) with parity support for ATM applications CSIX-L1 32-bit switch fabric interface (up to 100 MHz) Supports Generic 8,16,32-bit microprocessor bus interface for configuration, control and status monitoring Supports Generic 32, 64-bit peripheral bus interface for bridging functions
Flexible Programmable Logic
* 2,016 Programmable Logic Cells * 536 K System Gates * Muxed architecture; non-volatile technology * Completely customizable for any digital
application
Dual Port SRAM Blocks
* 36 Dual Port SRAM Blocks * Configurable array sizes (by 2, 4, 9, 18) * < 3 ns access times, FIFO capable of over
300 MHz * Configurable as RAM or FIFO
(c) 2002 QuickLogic Corporation
Preliminary
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QL82SD Device Data Sheet Rev C
Programmable I/O
* Up to 252 Programmable I/O pins * High performance Enhanced I/O (EIO): Less than 3 ns Tco * Programmable Slew Rate Control * Programmable I/O Standards * LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3, LVDS, LVPECL * Four Independent I/O Banks * Three Register Configuration: Input, Output, OE
Embedded Computational Unit (ECU) Blocks
* Integrated multiply, add, and accumulate function * 18 distributed MAC blocks *8 * 16-bit carry add
x 8 multiply (sign & unsigned)
Advanced Clock Network
* Nine Global Clock Networks consisting of: * one dedicated * eight programmable * Eight I/O (high drive) networks: two I/Os per bank * Ten Quad-Net Networks--five per quadrant
IO Block RAM Blocks IO Block IO Block
CH7
IO Block
Embedded Computational Units (ECUs)
2016 Logic Cells
RAM Blocks
LVDS/SERDES IO Block
CLKA CLKB CH3 CH4 CH0 CH1 CH2 CH5 CH6
Figure 1: QL82SD Device Block Diagram
Table 1: QL82SD Device Table Customer Part # QL82SD-PQ208 QL82SD-PT280 QL82SD-PS484 QL82SD-PB516 * * 2 * www.quicklogic.com * * * SERDES Data 4 8 8 8 LVDS Clocks 2 2 2 2 SRAM Blocks 36 36 36 36 Logic Cells 2016 2016 2016 2016 ECU Blocks 18 18 18 18 Programmable I/O 75 121 209 252
Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
General Description
LVDS SERDES Transmitter and Receiver
A QuickSD LVDS SERDES device in serializer mode takes a parallel data bus and a separate clock and converts them into a serial data stream. In deserializer mode, it takes a serial data stream and converts it to a configurable bit wide parallel data bus and separate clock. The reduced number of I/O board traces and cable connectors saves on cost and significantly simplifies design. Skew and timing issues are significantly reduced and performance is enhanced. Figure 2 and Figure 3 illustrate the block diagrams of the QuickSD device transmitter and receiver.
Parallel to Serial
RL = 27 - 100
300k Do + Do 300k
txd [9:0]
. . . .
Vo IL = 8-12 mA
Vo +
/Enable
Figure 2: LVDS SERDES Transmitter Block Diagram
Serial to Parallel FPGA 300k W Din + TTL_Din VCM = 0.2 V - 2.2 V
Din 300k W
. . . .
rxd [9:0]
Figure 3: LVDS SERDES Receiver Block Diagram
(c) 2002 QuickLogic Corporation
Preliminary
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QL82SD Device Data Sheet Rev C
LVDS SERDES Applications
The QuickSD device is designed to address the need for high-speed serial communications. It maintains the features of standard discrete SERDES devices, but integrates these features with customizable logic to allow for the highest degree of flexibility, performance, and integration at the lowest cost. The QuickSD device is designed to support both transmit and receive requirements in a single chip. The device can support multiple channels in a variety of modes (with or without clock recovery,) a variety of translation widths (1:1 to 1:10), as well as a range of frequencies. These capabilities make this device ideal in applications where the performance is critical and customization is required. The QuickSD device targets three applications: on-board, board-to-board (via common backplane), and box-to-box (via common cable).
Software Support
The turnkey QuickWorks package from QuickLogic provides the most complete ESP and FPGA software solution from design entry to logic synthesis, to place and route, and to simulation. The package provides a solution for designers who use third-party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic, Veribest and other third-party tools for design entry, synthesis, or simulation. A power calculator is also provided for SERDES power consumption. To speed up the QuickSD design process, QuickLogic includes a SERDES Wizard in its QuickWorks package. This wizard simplifies the process of configuring the multi-channel SERDES core into each of its modes. For details on the SERDES Wizard, please refer to "The QL82SD Quickstart Design Guide". To find this guide go to the QuickSD device documentation Web page at
htt p: //www.qui ck logi c.co m/ho me . asp?Pag eID =31 5&sMenuI D=1 99#Order.
Process Data
QuickSD is fabricated on a 0.25 , five-layer metal CMOS process. The core voltage is 2.5 Volt VCC supply and 3.3 V tolerant I/O with the addition of 3.3 Volt VCCIO. QuickSD is available in commercial and industrial temperature grades.
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Ordering Information
QL 82SD - 4 PB516 C QuickLogic device Operating Range C = Commercial I = Industrial M = Military Package Code PQ208 = 208-pin FPBGA PT280 = 280-pin BGA (1.0mm) PS484 = 484-pin BGA (1.0mm) PB516 = 516-pin BGA (1.27mm)
QuickSD device part number Speed Grade 4 = Quick 5 = Fast 6 = Faster 7 = Fastest
Maximum Ratings and Operating Range
Table 2: Absolute Maximum Electrical Ratings VCC Voltage LVCMOS/LVTTL Input Voltage LVCMOS/LVTTL Output Voltage Bus LVDS Receiver Input Voltage -0.3 V to 4 V -0.3 V to (VCC + 0.3 V) -0.3 V to (VCC + 0.3 V) -0.3 V to +2.8 V Bus LVDS Driver Output Voltage Bus LVDS Output Short Circuit Duration ESD Rating -0.3 V to +2.8 V 10 mS HBM 2 kV
Table 3: Absolute Maximum Thermal Ratings Junction Temperature +150C Lead Temperature (Soldering, 4 seconds) Thermal and Power Dissipation Characteristics +260C
Storage Temperature
-65C to +150C
See the following table
Table 4: Thermal and Power Dissipation Characteristics Package 0.0 PQ208 26.0 0ja (*C/W vs. Airflow 0.5 24.5 1.0 23.0 2.0 22.0 11.0 1.65 0jc (*C/W) Estimated Maximum Power Dissipation (W)
(c) 2002 QuickLogic Corporation
Preliminary
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QL82SD Device Data Sheet Rev C
Table 4: Thermal and Power Dissipation Characteristics Package 0.0 PT280 PS484 PB516 18.5 28.0 20.0 0ja (*C/W vs. Airflow 0.5 17.0 26.0 19.0 1.0 15.5 25.0 17.5 2.0 14.0 23.0 16.0 7.0 9.0 7.0 2.24 2.42 2.51 0jc (*C/W) Estimated Maximum Power Dissipation (W)
Table 5: Operating Ranges Symbol Parameter Industrial Min Vcc Vccio TA Supply Voltage I/O Input Tolerance Voltage Ambient Temperature -4 Speed Grade K Delay Factor -5 Speed Grade -6 Speed Grade -7 Speed Grade 2.3 2.3 -40 0.43 0.43 0.43 0.43 Max 2.7 3.6 85 2.16 1.80 1.26 1.14 Commercial Min 2.3 2.3 0 0.47 0.46 0.46 0.46 Max 2.7 3.6 70 2.11 1.76 1.23 1.11 V V C n/a n/a n/a n/a Unit
Electrical Specifications - LVDS SERDES
LVDS SERDES Transceiver Capability (Speed)
General Test Conditions
All tests are done for the 484-pin BGA package (1.00 mm pitch). The tests are set up so that an LVDS SERDES channel of a QL82SD transmits, and the other LVDS SERDES channel of the same device (or another QL82SD device) receives. All results are given as worst cases over commercial temperature, VCC, and process, with PLLVCC = 2.5 V unless otherwise specified. If the QL82SD device is used only for transmit or receive, but not both simultaneously, the performance can be significantly better, and, in many cases, exceeds 1 Gb/s per channel. NOTE: All data are in Mb/s. Low/High frequencey refers to internal SERDES PLL lock range (see Table 29 on page 31 for more information).
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Cable - Normal Operation
Table 6: Cable - Normal Low Frequency Modes 10:1 8:1 7:1 4:1 Min Max High Frequency Min 250 224 224 224 Max 350 368 364 304
Mode Not Available 112 112 112 360 322 348
NOTE: Test Conditions: Up to 3-meter Category 5 Cable without any compensation.
Cable - High Speed Operation
Table 7: Cable - High Speed Operation Low Frequency Modes 10:1 8:1 7:1 4:1 Min Max High Frequency Min 250 224 224 224 Max 350 552 504 500
Mode Not Available 112 112 112 480 462 456
NOTE: Test Conditions: Up to 9" Category 5 Cable, and reference design in the programmable fabric portion of the device for internal skew compensation for channel link modes.
Backplane - Normal Operation
Table 8: Backplane - Normal Operation Low Frequency Modes 10:1 8:1 7:1 4:1 Min Max High Frequency Min 250 224 224 224 Max 350 376 385 384
Mode Not Available 112 112 112 320 315 384
NOTE: Test Conditions: Up to 18" point-to-point backplane without any compensation.
(c) 2002 QuickLogic Corporation
Preliminary
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QL82SD Device Data Sheet Rev C
Backplane - High Speed Operation
Table 9: Backplane - High Speed Operation Low Frequency Modes 10:1 8:1 7:1 4:1 Min Max High Frequency Min 250 224 224 224 Max 350 632 630 628
Mode Not Available 112 112 112 632 630 628
NOTE: Test Conditions: Up to 18" point-to-point backplane, and reference design in the programmable fabric portion of the device for internal skew compensation for channel link modes.
1:1 Mode (Asynchronous Level Conversion)
Up to 9" cable: 0 to 500 Mbps Up to 18" point-to-point backplane: 0 to 700 Mbps All numbers are for LVDS channel performance only, and do not include the programmable fabric's ability to support high data rates.
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Bus LVDS DC Specifications
Over the operating range, RxVcc = 3.0 V to 3.6 V. NOTE: Apply to pad_ChX_p/n, pad_ClkX_p/n
Table 10: Serializer / Transmitter Symbol VOD VOS IOS Parameter Output Differential Voltage, pad_ChX_p - Pad_ChX_n Offset Voltage Output Short Circuit Current Conditions Figure 4 Figure 5 RL = 27 DO = 0 V, DIN + H, EN + OE + VCC DO = 0 V/VCC, EN = 0 VCC - 0 V, DO = 0 V/VCC Min 240 0.90 20 Typ 325 1.10 25 Max 420 1.30 35 Units mV V mA
IOZ IOX
Tri-State Output Current Power-Off Output Current
-25 -25
10 10
25 25
A A
Table 11: Deserializer / Receiver Symbol VTH VTL Parameter Differential Threshold High Voltage Differential Threshold Low Voltage Conditions Figure 6 VCM = 1.1 V VIN = 0 V, VCC = 0 V / 3.6 V VIN = 2.4 V, VCC = 0 V / 3.6 V Min n/a -50 -25 -25 Typ 35 -35 8 8 Max 50 n/a 25 25 Units mV mV A A
IIN
Input Current
D out +
D out Figure 4: Output Differential Voltage
(c) 2002 QuickLogic Corporation
Preliminary
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QL82SD Device Data Sheet Rev C
82SD BLVDS output Vod vs Iod 1.00 0.90 0.80 0.70 0.60 Vod ( v ) 0.50 0.40 0.30 0.20 0.10 0.00 8 9 10 Iod ( m A ) 11 12 13 27 60 100 80
40
Figure 5: Output Differential Voltage for Different Loads
VTH/ VTL
VCM
Figure 6: Differential Threshold Voltages
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Supply Current per Channel
Table 12: Serializer / Transmitter Symbol Parameter Conditions Figure 7 Figure 8 ICCT Serializer Supply Current CL =10 pF Figure 9 Figure 12 Figure 11 ICCTX Serializer Supply Current Powerdown 1:1 Mode 4:1 Mode 7:1 Mode 8:1 Mode 10:1 Mode Data/Clock Min Typ Figure 7 Figure 8 Figure 9 Figure 12 Figure 11 1 10 Max Units mA mA mA mA mA A
EN = 0
Table 13: Deserializer / Receiver Symbol Parameter Conditions Figure 13 Figure 14 ICCR Serializer Supply Current CL = 10 pF Figure 15 Figure 13 Figure 14 ICCRX Serializer Supply Current Powerdown 1:1 Mode 4:1 Mode 7:1 Mode 8:1 Mode 10:1 Mode Data/Clock Min Typ Figure 13 Figure 14 Figure 15 Figure 13 Figure 14 1 10 Max Units mA mA mA mA mA A
EN = 0
NOTE: More accurate supply current/power consumption numbers specific to your application should be calculated using the power calculator supplied with QuickLogic's QuickWorks software package.
(c) 2002 QuickLogic Corporation
Preliminary
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* * 11 * *
QL82SD Device Data Sheet Rev C
Supply Current at VccTx = 2.5 V 13 12 20 ICCT (mA) 11 10 9
Rt=100ohm Rt= 27ohm Rt=100ohm
25
Supply Current at VccTx = 2.5 V
ICCT (mA)
15
0
0
100
200 300 400 500 600 700 Clock Frequency(MHz)
10 10
Rt= 27ohm
30 50 Clock Frequency(MHz)
70
Figure 7: Data/Clock Channel, 1:1 Transmit Mode
Supply Current at VccTx = 2.5 V 20
Figure 10: Data/Clock Channel, 8:1 Transmit Mode
Supply Current at VccTx = 2.5 V
25
20 ICCT (mA) 15 ICCT (mA)
15
Rt=100ohm
10 20 40
Rt=100ohm Rt= 27ohm
Rt= 27ohm
10
60 80 100 120 140 Clock Frequency(MHz)
160
20
40 Clock Frequency(MHz)
60
Figure 8: Data/Clock Channel, 4:1 Transmit Mode
25 Supply Current at VccTx = 2.5V
Figure 11: Data/Clock Channel,10:1 Transmit Mode
Supply Current at VCCRX = 3.3 V VCC = 2.5 V 20 18 16
20 ICCT (mA) ICCR (mA)
Rt=100ohm Rt= 27ohm
14 12 10 8 6
15
10 10
4 2 0 100 200 300 400 500 600 700 Clock Frequency (MHz)
30 50 70 Clock Frequency(MHz)
90
Figure 9: Data/Clock Channel, 7:1 Transmit Mode
Figure 12: Data/Clock Channel, 1:1 Receive Mode
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
25
Supply Current at VCCRX = 3.3 V, VCC = 2.5 V
20
Supply Current at VCCRX = 3.3 V, VCC = 2.5 V
20 ICCR (mA) ICCR (mA)
15
15
10
10
5
5
0 20 40 60 80 100 120 140 Clock Frequency (MHz) 160 10 20 30 40 50 60 70 Clock Frequency (MHz) 80 90
Figure 13: Data/Clock Channel, 4:1 Receive Mode
20 Supply Current at VCCRX = 3.3 V, VCC = 2.5 V
Figure 15: Data/Clock Channel, 8:1 Receive Mode
20 Supply Current at VCCRX = 3.3 V, VCC = 2.5 V
15 15 ICCR (mA) ICCR (mA) 10
10
5
5
0 10
0 30 50 70 Clock Frequency (MHz) 90
20
25
30
35
40
45
50
55
60 70
Clock Frequency (MHz)
Figure 14: Data/Clock Channel, 7:1 Receive Mode
Figure 16: Data/Clock Channel, 10:1 Receive Mode
(c) 2002 QuickLogic Corporation
Preliminary
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* * 13 * *
QL82SD Device Data Sheet Rev C
SERDES Timing Requirements
NOTE: Both Table 14 and Table 15 refer to CDR (10:1) Mode for ChX_txclk and Channel Link (8:1, 7:1, 4:1) Mode for ClkX_txclk
Table 14: Serializer / Transmitter Transmit Clock Symbol tTCP tTDC tCLKT tJIT Parameter Transmit Clock Period Transmit Clock Duty Cycle Transmit Clock Input Transition Time Transmit Clock Input Jitter Figure 17 Conditions Mode Dependent Min n/a 45 1 n/a Typ T 50 n/a n/a Max n/a 55 n/a 150.0 Units nS % V/nS pS (RMS)
Table 15: Deserializer / Receiver Transmit Clock Symbol tRFCP tRFDC tRFCP/tTCP tRFTT Parameter Reference Clock Period Reference Clock Duty Cycle Ratio of Reference Clock to Transmit Clock Reference Clock Transition Time Figure 17 Conditions Mode Dependent Min n/a 40 0.4 1 Typ T 50 0.5 n/a Max n/a 60 0.6 n/a Units nS % n/a V/nS
90% txclk 10% tclkT/tRFTT
90% 10% tclkT/tRFTT
Figure 17: Serializer Transmit Clock / Deserializer Reference Clock Transition Times
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
SERDES Switching Characteristics - Serializer/Transmitter]
Table 16: Serializer/Transmitter Switching Characteristics CDR (10:1) Mode Symbol tHZD tLZD tZHD tZLD tDIS tDIH tPLD Parameter pad_ChX_p/n High to Tri-State Delay pad_ChX_p/n Low to Tri-State Delay pad_ChX_p/n Tri-State to High Delay pad_ChX_p/n Tri-State to Low Delay ChX_txd[9:0] Setup to ChX_txclk ChX_txd[9:0] Hold from ChX_txclk Serializer PLL Lock Time Figure 19 Figure 20 Figure 18 Conditions Min 1.9 1.9 1.9 2.0 2.6 2.1 Typ 2.2 2.0 2.4 2.3 Max 2.5 2.2 3.0 2.8 3.2 2.7 90 Units nS nS nS nS nS nS uS
Channel Link (8:1, 7:1, 4:1) Mode Symbol tHZD tLZD tZHD tZLD tDIS tDIH tSD tSCP tTXD[N-1] tPLD Parameter pad_ChX_p/n High to Tri-State Delay pad_ChX_p/n Low to Tri-State Delay pad_ChX_p/n Tri-State to High Delay pad_ChX_p/n Tri-State to Low Delay ChX_txd[N-1:0] Setup to ChX_txclk ChX_txd[N-1:0] Hold from ChX_txclk Serializer Delay Serial Transmit Clock Period Transmitter Output Pulse Position for Bit [N-1] Serializer PLL Lock Time Figure 20 [N-1] x tSCP + 1.1 Figure 21 T/mode [N-1] x tSCP + 1.5 90 Figure 18 Conditions Min 1.9 1.9 1.9 2.0 2.6 2.1 Typ 2.2 2.0 2.4 2.3 Max 2.5 2.2 3.0 2.8 3.2 2.7 1.7 Units nS nS nS nS nS nS nS nS nS uS
Asynchronous Level Conversion (1:1) Mode tHZD tLZD tZHD tZLD tASD tASC pad_ChX_p/n High to Tri-State Delay pad_ChX_p/n Low to Tri-State Delay pad_ChX_p/n Tri-State to High Delay pad_ChX_p/n Tri-State to Low Delay Asynchronous Serializer Delay Data Channel Asynchronous Serializer Delay Channel Clock Figure 18 1.9 1.9 1.9 2.0 2.2 2.0 2.4 2.3 2.5 2.2 3.0 2.8 1.8 Figure 22 1.7 nS nS nS nS nS nS
(c) 2002 QuickLogic Corporation
Preliminary
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QL82SD Device Data Sheet Rev C
EN
3V 0V V0H
1.5V t HZD
1.5V t ZHD
50%
t LZD 50% t ZLD
50%
1.1V 1.1V
Pad_p/n V 0L 50%
50%
Figure 18: Serializer Delays to Tri-State
Ch0_txclk t DIS Ch0_txd[9:0] A B C D E F
Pad_Ch0_p/n t DIH
Figure 19: 10:1 Mode Serializer Transmit with Embedded Clock
ENABLE
2.0V
0.8V t HZD or t LZD t ZHD or t ZLD
txclk
Pad_p/n
TRI-STATE
Output Active
TRI-STATE
Figure 20: Serializer PLL Times
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
ChX _ txd [7:0]
t DIS t DIH
ChX_txclk
t SD
Pad_ClkX_p/n
Pad_ ChX _p/n Note: t TXD [N-1] denotes physical bit positions wrt Pad_ClkX_p/n while Pad_ChX_p/n bit[n] refers to logical bit positions wrt ChX_txd [7:0].
t TXD [0] t TXD [4] t TXD [5] t TXD [6] t TXD [7]
[bit3] [bit2] [bit1] [bit0] [bit7] [bit6] [bit5] [bit4]
Figure 21: Channel Link Mode Serializer Transmit (Using 8:1 Mode as Example)
Ch0_txd [0]
t
ASD
Pad_Ch0_p/n
ClkA_txclk
t
ASC
Pad_ClkA_p/n
Figure 22: 1:1 Mode Asynchronous Level Conversion Mode Serializer Delays
(c) 2002 QuickLogic Corporation
Preliminary
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* * 17 * *
QL82SD Device Data Sheet Rev C
SERDES Switching Characteristics - Deserializer/Receiver
Table 17: Deserializer / Receiver Switch Characteristics CDR (10:1) Mode Symbol tRCP tRDC tDD tRXPD tDSR1 tDSR2 tDJIT Parameter
ChX_rxclk Period ChX_rxclk Duty Cycle Deserializer Delay Figure 23 ChX_rxclk to ChX_rxd[9..0] Deserializer PLL Lock Time from powered-down state Figure 24: 25 MHz Figure 24: 50 MHz Figure : 25 MHz Deserializer PLL Lock Time from SYNCPAT Figure : 50 MHz Pad_ChX_p/n Jitter 25 MHz 50 MHz 1.5 2.5 5 8 1 0.75 3.5 nS uS uS uS uS pS pS 2
Conditions
Min
28.5 45
Typ
T 50 2
Max
40.0 55 2
Units
nS % nS
x tRCP + 1.5
x tRCP + 2.5
x tRCP + 3.5
350 200
Min
Mode Dependent -1 LVDS Link Frequency Compression Mode
Channel Link (8:1, 7:1, 4:1) Mode Symbol Parameter Conditions Typ Max
Mode Dependent -1 LVDS Link Frequency Compression Mode
Units
tRCP
ChX_rxclk Period
T
nS
tRDC tDD tRXPD tRXDS tRXDH tSCD tSCP tRXD[N-1] tDSR1 tDJIT
ChX_rxclk Duty Cycle Deserializer Delay ChX_rxclk to ChX_rxd[N-1..0] Pad_ChX_p/n Setup to Strobe Position Figure 26 Pad_ChX_p/n Hold to Strobe Position Pad_ClkX_p/n to Serial Clock Delay Serial Clock Period Receiver Input Strobe Position for Bit [N-1] Deserializer PLL Lock Time from powered-down state Pad_ChX_p/n Jitter Figure 24: 25 MHz Figure 24: 50 MHz 25 MHz 50 MHz a 2
45
50 2
55 2
% nS nS pS pS nS nS
x tRCP + 1.5
1.5
x tRCP + 2.5
2.5 150 150
x tRCP + 3.5
3.5 200 200 1
0.6
0.8 T/mode
[N-1] x tSCP + 1.1 5 8
[N-1] x tSCP + 2.4
nS uS uS pS pS
300 150
Asynchronous Level Conversion (1:1) Mode tADD tADC
Asynchronous Deserializer Delay Data Channel Figure 27 Asynchronous Serializer Delay a Channel Clock 0.6 0.8 1 nS 1.7 nS
a. These values include the delay resulting from application of internal compensation for data/clock skew.
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
pad_Ch0_p/n
t DD
Ch0_rxclk t RXPD Ch0_rxd[9:0]
A B
Ch0_txclk
Figure 23: 10:1 Mode Deserializer Receive with Embedded Clock
2.0V
Enable Chx_txclk
t DSR1 Data
0.8V 1.5V
Pad_Chx_p/n
t ZHLK SYNC patterns t ZHR or t ZLR
SYNC Symbol or DIN0-9
Chx_lock Chx-rxd [N-1,0] Chx_rxclk OE
t HZR or t LZR
Figure 24: Deserializer PLL Lock Time from Power Down
VCC Enable 0.8V Chx_txclk t Pad_Chx_p/n SYNC patterns Chx_lock Chx-rxd [N-1,0] t ZHR or t ZLR
SYNC Symbol or DIN0-9
0.0V
DSR2
Data
1.2V 1.0V
t
HZR or t LZR
Chx_rxclk OE
Figure 25: 10:1 Mode Deserializer PLL Lock Time from SYNCPAT
(c) 2002 QuickLogic Corporation www.quicklogic.com * *
* * 19 * *
Preliminary
QL82SD Device Data Sheet Rev C
t
RCP
Pad_Clkx_p/n
t RXD t RXD t RXD t RXD [1] max [1] min [0] max [0] min t SCP
Note: t RXD [N-1] denotes
physical strobe positions wrt Pad_ClkX_p/n while Pad_ChX_p/n bit[n] refers to logical bit positions wrt ChX_rxd [7:0].
SerialClock (Internal) Pad_ Chx_p/n
t SCD
Strobe [bit3] [bit2] [bit1] [bit0] [bit7] [bit6] [bit5] [bit4]
RXDS t RXDH
t
Chx_ [7:0] rxd Chx _rxclk
t DD t RXPD
Figure 26: Channel Link Mode Deserializer Receive (Using 8:1 Mode as Example)
Ch0_txd [0]
t
ASD
Pad_Ch0_p/n
ClkA_txclk
t
ASC
Pad_ClkA_p/n
Figure 27: 1:1 Mode Asynchronous Level Conversion Mode Deserializer Delays
SERDES Bit Error Rate
The following table indicates the SERDES bit error rate at TA = 25 C and PLLVcc = 2.5 V unless otherwise specified.
Table 18: Serializer/Deserializer Bit Error Rate Modes 10:1 8:1 7:1 4:1 * * 20 * www.quicklogic.com * * * Bit Error Rate < 1 x 10-12 < 1 x 10-12 < 1 x 10-12 < 1 x 10-12
Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Electrical Specification - Programmable Fabric
DC Characteristics
Table 19: DC Characteristics Symbol II IOZ CI IOS Parameter I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance
a
Conditions VI = VCCIO or GND VI = VCCIO or GND
Min -10 -10
Max 10 10 8
Units A A pF mA mA mA mA A A
Output Short Circuit Current b
Vo = GND Vo = VCC
-15 40 0.50 (typ) 0 -10
-180 210 2 2 10 150
ICC ICCIO IREF IPD
D.C. Supply Current
c
VI,Vo =VCCIO or GND
D.C. Supply Current on VCCIO D.C. Supply Current on VREF Pad Pull-down (programmable) VCCIO = 3.6 V
a. Capacitance is sample tested only. Clock pins are 12 pF maximum. b. Only one output at a time. Duration should not exceed 30 seconds. c. For -4/-5/-6/-7 commercial grade devices only. Maximum ICC is 3 mA for all industrial grade devices.
DC Input/Output Levels
Table 20: DC Input/Output Levels VREF VMIN LVTTL LVCMOS2 GTL+ PCI SSTL2 SSTL3 n/a n/a 0.88 n/a 1.15 1.30 VMAX n/a n/a 1.12 n/a 1.35 1.70 VMIN VIL VMAX 0.8 0.7 VREF - 2.0 VMIN 2.0 1.7 VREF + 2.0 VIH VMAX VCCIO - 0.3 VCCIO - 0.3 VCCIO - 0.3 VOL VMAX 0.40 0.70 0.60 VOH VMIN 2.40 1.70 n/a IOL mA 2.0 2.0 40 1.5 7.6 8.0 IOH mA
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3
-2.0 -2.0
n/a
0.30 x VCC 0.50 x VCC VCCIO - 0.5 0.10 x VCC 0.90 x VCC VREF - 0.18 VREF + 0.18 VCCIO + 0.3 VREF - 0.20 VREF + 2.0 VCCIO + 0.3 0.74 1.10 1.76 1.90
-0.5 -7.6 -8.0
NOTE: The above table gives the programmable logic timing model for the QuickSD device. The programmable logic includes the following major elements: Super Logic (Flip-Flop and Combinational Circuit), Clock, and I/O.
(c) 2002 QuickLogic Corporation
Preliminary
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* * 21 * *
QL82SD Device Data Sheet Rev C
Super Logic (Flip-Flop and Combinational Circuit) AC Characteristics at VCC = 2.5 V, TA = 25o C (K = 1)
set d clk reset q
Figure 28: Super Logic Cell Flip-Flop Structure
Table 21: Logic Cells Propagation delay (ns) Symbol Parameter Condition Fanout = 1
tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW
Combinational Delay a Setup Time Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width
b
Figure 29 Figure 30 Figure 31 Figure 32
0.257 0.22 0 0.255 0.46 0.46 0.18
Figure 33
0.09 0.30 0.30
a. Stated timing for worst case Propagation Delay over process variation at VCC = 2.5 V and TA = 25 C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the operating range. b. These limits are derived from a representative selection of the slowest paths through the logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
input output
tPD
Figure 29: Combinational Delay for Logic Cell
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Input (d) clk tSU tH
Figure 30: Setup and Hold Time for Flip-Flop
Figure 31: Delay from Clock Input to Flip-Flop Q Output
Figure 32: Clock High and Low Time for Flip-Flop
Figure 33: Timing Requirements for Flip-Flop SET and RESET
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Preliminary
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* * 23 * *
QL82SD Device Data Sheet Rev C
Clock AC Characteristics at VCC = 2.5 V, TA = 25 oC (K = 1)
Global Clock Buffer programmable clock Hardware Clock Global Clock
tPGCK
tBGCK
Figure 34: Clock Structure
Table 22: Clock Performance Clock Performance Global Logic Cells I/Os Skew 1.51 ns 2.06 ns 0.55 ns Table 23: Input Register Cell Symbol Input Register Cell Only tPGCK tBGCK Parameter Global clock pin delay to quad net Global clock buffer delay (quad net to flip flop) Propagation Delay (ns) 1.34 0.56 Dedicated 1.59 ns 1.73 ns 0.14 ns
I/O AC Characteristics at VCC = 2.5 V, TA = 25 oC (K = 1)
Figure 35: I/O Structure
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
TICLK TIN, TINI TISU + tSID D
QE R
PAD
Figure 36: Input Register Cell
Table 24: Input Register Cell Symbol Input Register Cell Only tISU tIH tICLK tIRST tIESU tIEH Input Register Setup Time: the amount of time the synchronous input of the flip flop must be stable before the active clock edge. Input Register Hold Time: the amount of time the synchronous input of the flip flop must be stable after the active clock edge. Input Register Clock to Q: the amount of time taken by the flip flop to output after the active clock edge. Input Register Reset Delay: the amount of time between when the flip flop is "reset" (low) and when Q is consequently "reset" (low). Input Register Clock Enable Setup Time: the amount of time "enable" must be stable before the active clock edge. Input Register Clock Enable Hold Time: the amount of time "enable" must be stable after the active clock edge. 3.12 0 1.08 0.99 0.37 0 Parameter Propagation Delay (ns)
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Preliminary
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* * 25 * *
QL82SD Device Data Sheet Rev C
Table 25: Standard Input Delays Symbol Standard Input Delays tSID (LVTTL) tSID (LVCMOS2) tSID (GTL+) tSID (SSTL3) tSID (SSTL2) Parameter To get the total input delay and this delay to tISU LVTTL input delay: Low Voltage TTL for 3.3 V applications LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower applications GTL+ input delay: Gunning Transceiver Logic SSTL3 input delay: Stub Series Terminated Logic for 3.3 V SSTL2 input delay: Stub Series Terminated Logic for 2.5V 0.34 0.42 0.68 0.55 0.607 Propagation delay (ns)
R CLK
D Q
tISU
tIH tICLK tIRST
E
tIESU tIEH
Figure 37: Input Register Timing
PAD OUTPUT REGISTER
Figure 38: Output Register Cell
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Table 26: Output Register Cell Symbol Output Register Cell Only tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ tCO Output Delay low to high (10% of H) Output Delay high to low (90% of H) Output Delay tri-state to high (10% of Z) Output Delay tri-state to low (90% of Z) Output Delay high to tri-State Output Delay low to tri-State Clock to out delay 0.40 0.55 2.94 2.34 3.07 2.53 3.15 (fast slew) 10.2(slow slew) Parameter Propagation delay (ns)
H L H Z L H Z L tPZH
H L H Z L H Z L
tOUTHL
tOUTLH
tPZL tPHZ
tPLZ
Figure 39: Output Register Cell Timing
Electrical Specification - RAM Block
[9:0] [17:0]
WA WD WE WCLK RCLK
RE
RA RD ASYNCRD
[9:0] [17:0]
[1:0]
MODE
Figure 40: RAM Module
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Preliminary
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* * 27 * *
QL82SD Device Data Sheet Rev C
RAM Cell Synchronous Write Timing
Table 27: RAM Cell Synchronous Write Timing Symbol tSWA tHWA tSWD tHWD tSWE tHWE tWCRD Parameter WA setup time to WCLK: the amount of time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK WA hold time to WCLK: the amount of time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK WD setup time to WCLK: the amount of time the WRITE DATA must be stable before the active edge of the WRITE CLOCK WD hold time to WCLK: the amount of time the WRITE DATA must be stable after the active edge of the WRITE CLOCK WE setup time to WCLK: the amount of time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK WE hold time to WCLK: the amount of time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK WCLK to RD (WA=RA): the amount of time between the active WRITE CLOCK edge and the time when the data is available at RD Propagation delay (ns) 0.675 0 0.654 0 0.623 0 4.38
WCLK
WA tSWA WD tSWD tHWD tHWA
WE tSWE RD old data tWCRD tHWE new data
Figure 41: RAM Cell Synchronous Write Timing
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
RAM Cell Read Timing
Table 28: RAM Cell Synchronous and Asynchronous Read Timing Symbol Parameter Propagation delay (ns)
RAM Cell Synchronous Read Timing tSRA tHRA tSRE tHRE tRCRD RA setup time to RCLK: the amount of time the READ ADDRESS must be stable before the active edge of the READ CLOCK RA hold time to RCLK: the amount of time the READ ADDRESS must be stable after the active edge of the READ CLOCK RE setup time to WCLK: the amount of time the READ ENABLE must be stable before the active edge of the READ CLOCK RE hold time to WCLK: the amount of time the READ ENABLE must be stable after the active edge of the READ CLOCK RCLK to RD: the amount of time between the active READ CLOCK edge and the time when the data is available at RD 0.686 0 0.243 0 4.38
RAM Cell Asynchronous Read Timing rPDRD RA to RD: amount of time between when the READ ADDRESS is input and when the DATA is output 2.06
RCLK
RA TSRA THRA
RE TSRE THRE
RD
OLD data
NEW data
TRCRD
RPDRD
Figure 42: RAM Cell Synchronous and Asynchronous Read Timing
(c) 2002 QuickLogic Corporation
Preliminary
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* * 29 * *
QL82SD Device Data Sheet Rev C
LVDS SERDES Description
LVDS SERDES Applications
The QL82SD device in the QuickLogic QuickSD ESP (Embedded Standard Product) device family provides a completely integrated configurable Serializer/Deserializer interface solution combined with 536 K system gates of customizable logic. This device provides a means to receive and transmit high-speed serial data and implement any proprietary high-speed serial link. The QL82SD device is a high performance serializer/deserializer chip. It can be combined with FIFO buffer memory to build a complete serial link. The need for external FIFOs can be eliminated by configuring the available internal RAM as two 256 x 36 FIFOs. The embedded SERDES core is a full duplex design with a serialization section for transmission and a deserialization section for reception. The transmitter and receiver can be configured for level conversion (1:1), signals that transmit a clock signal with the data (1:4, 1:7, 1:8), or applications that require clock recovery (1:10). The embedded SERDES core has a system interface that emulates a synchronous FIFO for ease of use. FIFOs allow maximum sustained performance of 600 MB/s running a full duplex link. Their function is to handle the asynchronous interface between the bus data rate and the different serial data rates, and handle phase and frequency differences inherent in serial links. Internal FIFOs of 256 x 36 or 512 x 16 can be cascaded with external FIFOs to expand the buffering to the desired size. The QL82SD is a versatile part that allows the system designer to create proprietary or standardized serial links by taking advantage of some, or all, of the embedded features. It has a number of useful features for system designers of proprietary links with additions of embedded computational units and customizable I/O.
LVDS SERDES Block Functional Description
The QuickSD SERDES consists of a physical layer for high-speed serial communications, handling all data translations, clocking and timing. The core is made up of eight data channels and two channel clocks. These blocks contain the circuitry necessary for all the data muxing and de-muxing, clock multiplication and division, clock and data phase alignment, and clock recovery and encoding. The core can be configured to support systems that transmit a separate clock signal or that have the clock embedded into the data stream and require clock recovery.
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
LVDS SERDES Data Channel Configuration
A representation of the SERDES data channel is shown in Figure 43. The device consists of eight identical data channels.
Ch0_rst Ch0_oe Ch0_en Ch0_pre_emp Ch0_sync Ch0_mode[3:0] Ch0_txd[9:0] Ch0_txclk Ch0_lock
SERDES Channel 0
Ch0_rxd[9:0] Ch0_rxclk
pad_Ch0-p pad_Ch0_n
Figure 43: SERDES Channel 0
Each SERDES data channel can be operated independently. The data channels are transceivers, so they can either send or receive data on the serial LVDS wire pair. The direction of transfer is selected with the ChX_oe pin. If this pin is high, the channel is in transmit mode, if this pin is low, the channel is in receive mode. The data channel can be configured to deal with different parallel data widths and clocking mechanisms, Table 29 shows the settings for the ChX_mode[3:0] pins and the modes that they refer to. For the Channel Clock A/B modes, see "LVDS SERDES Channel Clock Configuration" on page 32 for more details. If the data channel is not needed, then it can be powered down (to reduce overall device power) by tying the ChX_en signal low. This signal must be held high for normal operation. For a detailed description of how to use the various modes of the data channel to transmit and receive data, see "LVDS SERDES Transmit and Receive Operation" on page 33.
Table 29: ChX_mode[3:0] ChX_mode[3] Description Low Frequency (1), High Frequency (0) bit [3] Determines high or low frequency lock range for internal SERDES PLL. When this bit is set to `1', the low frequency range is selected. When this bit is set to `0', the high frequency range is selected. In 10:1 mode, this bit must be set to `0'. In channel clock mode, the pin setting does not matter. Embedded clock mode (0), channel-clock (1) CLKA (1), CLKB (0) channel clock select
bit [2] bit [1] bit [0]
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Preliminary
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* * 31 * *
QL82SD Device Data Sheet Rev C
LVDS SERDES Channel Clock Configuration
There are two SERDES channel clocks within the core. Figure 44 shows a representation of the channel clock. Each channel clock is identical.
ClkA_oe ClkA_en ClkA_pre_emp ClkA_mode[1:0] ClkA_txclk ClkA_rxclk
SERDES CLKA
pad_ClkA_p pad_ClkA_n
Figure 44: SERDES CLK A
Each of the two SERDES channel clocks can be configured independently. They can be configured to act as the transmit or receive clock for up to 8 SERDES data channels (for serial links where the clock is provided as a separate LVDS wire pair). Alternatively, the channel clock can be configured as a simple bi-directional IO pin, where the internal signals are CMOS, but the external pin is LVDS. In such a case, the I/O will act simply as a level converter. Since the channel clock may act as a transmit or receive clock (or as an input or output signal in data mode), the direction of the channel clock must be selected with the ClkX_oe pin. If this pin is high, then the channel clock is transmitting a clock (or acting as an output signal in data mode). If this pin is low, then the channel clock is receiving a clock (or acting as an input signal in data mode). When the channel clocks are used to act as the transmit or receive clock for one or more data channels, then four modes are available, using the CLKx_MODE[1:0] input. Table 30 shows these modes.
Table 30: ClkX_mode[1:0] ClkX_mode[1:0] 00 01 10 11 Mode 1:1 mode (no PLL) 4:1 mode 7:1 mode 8:1 mode
When a channel clock is configured with ClkX_MODE[1:0] equal to 01, 10, or 11, then any of the data channels can be configured to use that channel clock as its clock, by setting the data channel's ChX_MODE inputs to point to the correct channel clock. See the Section , "LVDS SERDES Data Channel Configuration," on page 31 for more information. When the channel clock is configured with ClkX_MODE[1:0] equal to 00, the channel clock becomes a simple LVDS-to-CMOS level converter. When ClkX_oe is high, the channel clock will be configured as an output, in which the data supplied on the ClkX_txclk pin is converted to LVDS and comes out on the pad_ClkX_p and pad_ClkX_n external LDVS signals asynchronously. When ClkX_oe is low, the channel clock is configured as an LVDS input, in which the LVDS signal on pad_ClkX_p and pad_ClkX_n is converted to CMOS levels and enters the device on the ClkX_rxclk pin.
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Any data channel can also be configured as a level translator. This is done by setting that data channel's ChX_mode[3:0] input to point to a channel clock (A or B) which has also been configured in level translator mode.
LVDS SERDES Transmit and Receive Operation
The SERDES core can transmit and receive serial data across LVDS wires in many different formats. This section describes each of the various transmit and receive formats.
Transmit 10-bit Data With Embedded Clock
The waveform in Figure 19, illustrates how 10-bit data can be transmitted serially on the differential LVDS outputs. NOTE: The pad_ChX_p and pad_ChX_n outputs in the diagram are representing the data changes which occur on a pair of LVDS signals. When the SERDES is in 10-bit mode, no separate clock signal is needed, since the clock is embedded within the serial data stream. In Figure 19, you will notice that at tDIS the rising edge of ChX_txclk registers the 10-bit data value B within the SERDES core. After about one clock period of ChX_txclk, the serialized data begins to appear on the LVDS outputs (pad_ChX_p and pad_ChX_n) in the following sequence:
1. First, a logic 1 is transmitted, which is the start bit, and part of the data used to transmit
the clock.
2. Then each of the 10 bits of the data value B is transmitted in sequence. 3. Finally, a logic 0 is transmitted, which is the stop bit (MSB first). This stop bit is the
remaining part of the embedded clock. NOTE: By using a stop bit value of 0 and a start bit value of 1, there is always a guaranteed 0 to 1 transition in the bitstream (the end of one frame and the beginning of the next). Because of this, the receiver is able to recover the embedded clock from the serial bit stream. The pertinent timing parameters shown in Figure 19 are:
tDIS is the setup time needed for the ChX_txd bus relative to the ChX_txclk clock * tDIH is the hold time for the ChX_txd relative to the ChX_txclk clock
*
Receive 10-bit Data With Embedded Clock
In 10-bit mode, the clock is embedded in the serial data stream on the pad_ChX_p and pad_ChX_n LVDS signal (shown in Figure 23) as one signal, but actually is a pair of differential signals). When using the SERDES data channel in 10-bit receive mode, a reference clock is needed which matches the parallel clock rate of the transmitter (shown in Figure 23 as ChX_txclk). There is no timing phase relationship between the reference clock and the received parallel clock (ChX_rxclk), but the two clocks will have the same frequency. NOTE: The serial data bits are transmitted with a 0 as a stop bit and a 1 as a start bit, and. The SERDES block recovers the clock from this data stream, as shown with the ChX_rxclk waveform (Figure 23). The parallel 10-bit data is also recovered and timed appropriately with the recovered clock. The pertinent timing parameters shown in Figure 23 are:
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Preliminary
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QL82SD Device Data Sheet Rev C * *
edge of the recovered parallel clock recovered clock.
tDD is the delay from the rising edge of the start bit in the serial bitstream to the rising tRXPD is the propagation delay time provided for the recovered data with respect to the
Transmit 8-bit Data With Channel Clock
When the SERDES is in 8-bit mode, it must be configured to use a channel clock. The waveforms shown in Figure 21 show the parallel transmit clock provided by the user to the clock channel (ClkX_txclk), and the converted channel clock on the LVDS outputs of the channel clock (pad_ClkX_p and pad_ClkX_n). NOTE: The output of the channel clock has the same period as the parallel transmit clock. This is done to frame the serial data transmitted on the pad_ChX_p and pad_ChX_n pins. The LVDS channel clock (pad_ClkX_p and pad_ClkX_n) is multiplied up by the receiver to capture each bit of the transmitted data. The 8-bit data is converted to a simple serial bit stream. The pertinent timing parameters shown in Figure 21 are:
* * * *
tDIS is the setup time needed on the parallel transmit data (ChX_txd[7:0] with respect to the parallel transmit clock (ClkX_txclk)
the parallel transmit clock (ClkX_txclk) edge of the LVDS channel clock
tDIH is the hold time needed on the parallel transmit data (ChX_txd[7:0] with respect to tSD is the clock delay between the rising edge of the parallel transmit clock to the rising tTXD[N-1] is the serial data physical bit position with respect to the LVDS channel clock.
NOTE: tTXD[N-1] denotes physical bit positions wrt pad_ClkX_p/n while pad_ChX_p/n bit[n] refers to logical bit positions wrt ChX_txd[7:0].
Receive 8-bit Data With Channel Clock
The SERDES in 8-bit receive mode receives serial data on the pad_ChX_p and pad_ChX_n LVDS input, and a clock on the pad_ClkX_p and pad_ClkX_n LVDS input (see Figure 26 ). The LVDS input clock is multiplied by 8 within the SERDES core to capture the 8 bits of data from the pad_ChX_p and pad_ChX_n serial bitstream. The parallelized data goes out on the ChX_rxd internal 8-bit bus, and the re-timed parallel clock goes out on the ClkX_rxclk pin. The pertinent timing parameters shown in this diagram are:
* * * *
tDD is the delay between the first bit of the serial data showing up in the serial bit stream and the rising edge of the retimed parallel clock corresponding to the same data frame tRXPD is the propagation delay time provided for the recovered data with respect to the
recovered clock
LVDS inputs to the rising edge of the internal serial clock strobe
tRXDS is the setup time needed for the serial data on the pad_ChX_p and pad_ChX_n
tRXDH is the hold time needed for the serial data on the pad_ChX_p and pad_ChX_n LVDS inputs relative to the internal serial clock strobe
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Preliminary
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QL82SD Device Data Sheet Rev C * *
tSCD is the delay between the rising edge of the LVDS channel clock and the first rising
edge of the multiplied internal serial clock corresponding to the same data frame.
tRXD[N-1] is the internal clock strobe positions with respect to the rising edge of the LVDS channel clock
NOTE: tRXD[N-1] denotes physical strobe positions with respect to pad ClkX_p/n while pad_ChX_p/n bit[n] refers to logical bit positions with respect to ChX_rxd[7:0]
Asynchronous Level Conversion Mode for the Data Channel and Channel Clock
When the SERDES data channel ChX_mode[3:0] pins are set to use a channel clock which is in level translator mode, then that data channel is also in level translator mode. In level translator mode, the data channel only converts the internal CMOS signal to LVDS (for output mode), or vice versa for input mode. When the data channel or channel clock is in this asynchronous signal translation mode, and configured as outputs (ChX_oe or ClkX_oe high) the output mode waveforms in Figure 22 apply. When the data channel or channel clock is in this asynchronous signal translation mode, and configured as inputs (ChX_oe or ClkX_oe low) the input mode waveforms in Figure 27 apply.
Programmable Fabric Description
The QuickSD device features an enhanced Super Logic Cell with an additional D flip-flop register and associated control logic. This advanced architectural approach addresses today's highly register intensive designs. The QuickSD logic Supercell structure, shown in Figure 45, is similar to the .35 mm QuickLogic logic cell with the addition of a second register. Both registers share CLK, SET and RESET inputs. The second register has a two-to-one multiplexer controlling its input. This register can be loaded from the NZ output or directly from a dedicated input. NOTE: The input "PP" is not an "input" in the classical sense. It can only be tied high or low using default links only and is used to select which path "NZ" or "PS" is used as an input to the register. All other inputs can be connected not only to "tiehi" and "tielo" but to multiple routing channels as well. The complete logic cell consists of two 6-input AND gates, four two-input AND gates, seven two-to-one multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30 (including register control lines) and fits a wide range of functions with up to 17 simultaneous inputs. It has six outputs, of which four are combinatorial and two are registered. The high logic capacity and fan-in of the logic cell accommodate many user functions with a single level of logic delay while other architectures require two or more levels of delay.
(c) 2002 QuickLogic Corporation
Preliminary
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* * 35 * *
QL82SD Device Data Sheet Rev C
QS A1 A2 A3 A4 A5 A6 OS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 PS PP QC QR
AZ
OZ QZ
NZ Q2Z FZ
Figure 45: SERDES Logic Cell
RAM Block Description
General Description
The QuickSD device includes multiple dual-port 2,304-bit RAM modules for implementing RAM and FIFO functions. Each module is user-configurable into four different block organizations. Modules can also be cascaded horizontally to increase their effective width or vertically to increase their effective depth as shown in the following figure. The RAM can also be configured as a modified Harvard Architecture, similar to those found in DSPs.
2,304-bit Module MODE [1:0] ASYNCRD WA [9:0] WD [17:0] WE WCLK RA [9:0] RD [17:0] RE RCLK
Figure 46: SERDES 2,304-bit RAM Module
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
There are 36 RAM blocks within the QuickSD device, for a total of 82.9 Kbits of RAM. Using two "mode" pins, designers can configure each module into 128 x 18 (Mode 0), 256 x 9 (Mode 1), 512 x 4 (Mode 2), or 1024 x 2 blocks (Mode 3). The blocks are also easily cascadable to increase their effective width and/or depth. See Figure 47 for cascaded RAM modules.
WDATA WADDR
RAM Module
(2304 bits)
RDATA RADDR
RAM Module
WDATA
(2304 bits)
RDATA
Figure 47: Cascaded RAM Modules
The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE ports support synchronous operation. Each port has 18 data lines and 10 address lines, allowing word lengths of up to 18 bits and address spaces of up to 1,024 words. Depending on the mode selected, however, some higher order data or address lines may not be used. The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for asynchronous READ operation (ASYNCRD input high). Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. A similar technique can be used to create depths greater than 512 words. In this case address signals higher than the ninth bit are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals. The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions). The RAM achieve 155 MHz performance for the lowest speed grade devices when using multiple blocks cascaded together.
Multiple Accessing of Memories
The extremely fast RAM can be used in designs that require multiple memory accessing. The RAM achieves 280 MHz performance for the fastest speed grade and 155 MHz performance for the lowest speed grade devices when using multiple blocks cascaded together. Write through of DATA is also possible with the QuickLogic RAM.
(c) 2002 QuickLogic Corporation
Preliminary
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* * 37 * *
QL82SD Device Data Sheet Rev C
ECU Block Description
ECU Block General Description
Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively. These functions require high logic cell usage while garnering only moderate performance results. By embedding a dynamically reconfigurable computational unit, the QuickSD device can address various arithmetic functions efficiently and effectively providing for a robust DSP platform--this approach offers greater performance than traditional programmable logic implementations. The ECU block is ideal for complex DSP, filtering, and algorithmic functions. The QuickSD device architecture will allow functionality above and beyond that achievable using DSP processors or programmable logic devices. The embedded block is implemented at the transistor level with the following block diagram.
16 8 8 8 Multiply 8 16 Add 16 Register 3 1 17
Abus Xbus Ybus
Ibus Sign
Rbus
Sequencer
Memory
Logic Cell
Figure 48: SERDES ECU Block Diagram
ECU Mode Select
Table 31: Instruction Set Sequencer Instruction Set 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Operation Multiply Multiply - Add Accumulate Add Multiply (registered)
a
Multiply - Add (registered) Multiply Accumulate Add (registered)
a. A[15:0] set to zero.
The ECU block can be configured for eight arithmetic functions via an instruction as shown in Table 31. The modes for the ECU block are Dynamically Re-programmable through the Instruction Set Sequencer.
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Preliminary
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QL82SD Device Data Sheet Rev C
Clock Networks Description
Global Clocks
In the QuickSD device, there are nine global clock networks: one is dedicated and eight are programmable . Global clocks can drive logic cell, I/O, ECU blocks and RAM registers in the device. Five global clocks will have access to a Quad Net (local clock network) connection with a programmable connection to the register inputs. Figure 49 gives the global clock methodology
Figure 49: Global Clock
Quad-Net Network
There are five Quad-Net local clock networks in each quadrant for a total of 20 in a device. Each Quad-Net is local to a quadrant. Quad-Net is multiplexed with the clock buffer before driving the column clock buffers.
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Preliminary
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* * 39 * *
QL82SD Device Data Sheet Rev C
Dedicated Clock
There is one dedicated clock in QuickSD devices. It connects to the clock input of the SuperCell, I/O, and RAM registers through a hardwired connection and is multiplexed with the programmable clock input. There are four inversions from pad to register inputs and the dedicated clock takes on the same configuration as the global clock. The dedicated clock provides a fast global network with low skew. You can select either the dedicated clock or the programmable clock; Figure 50 gives the dedicated clock circuitry within the logic cell.
Programmable clock Hard-wired clock
CLK
Figure 50: Dedicated Clock Circuitry
The performance of the dedicated clock is given in Table 32
Table 32: Dedicated Clock Performance Clock Performance TT, 25C, 2.5 V Macro (rear) I/O (far) Skew Global 1.51 2.06 0.55 Dedicated 1.59 1.73 0.14
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
I/O Cell Structure
I/O Cell Structure General Description
The QuickSD device features a variety of distinct I/O pins to maximize performance, functionality, and flexibility with bi-directional I/O pins and input-only pins. All input and I/O pins are 2.5 V and 3.3 V tolerant and comply with the specific I/O standard selected. The outputs swing from Vss to VCCIO (0 V to 3.3 V 10%). The VCCIO pins must be tied to a 3.3 V supply to provide 3.3 V compliance. If 3.3 V compliance is not required, then these pins must be tied to the 2.5 V supply. Table 33 summarizes the I/O specifications that are supported.
Table 33: Supported I/O Specifications /O Standard Reference Voltage Output Voltage LVTTL LVCMOS2 PCI GTL+ SSTL3 SSTL2 n/a n/a n/a 1 1.5 1.25 3.3 2.5 3.3 n/a 3.3 2.5 Application general purpose general purpose PCI bus applications high speed bus - Pentium Pro memory bus - Hitachi, IBM memory bus - Hitachi, IBM
As designs become more complex and requirements more stringent, varying I/O standards are developing for specific applications. I/O standards for processors, memories and various bus applications have become common place and a requirement for many systems. In addition, I/O timing has become a greater issue with specific requirements for setup, hold, clock to out, and switching times. The QuickSD device has addressed these changing system requirements. The QuickSD device includes a completely new I/O cell which consists of programmable I/Os as well as a new cell structure consisting of three registers: input, output and output enable. The QuickSD device offers banks of programmable I/O that addresses many of the new bus standards that are popular today. In addition, the input register addresses the setup time, the output register addresses clock-to-out time, and the OE register addresses the switching time from high impedance to a given value.
Figure 51 shows the QuickSD device I/O cell.
(c) 2002 QuickLogic Corporation
Preliminary
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* * 41 * *
QL82SD Device Data Sheet Rev C
+ Q E R E R D
D
Q
PAD
D
E R
Q
Figure 51: QuickSD I/O Cell
The bi-directional I/O pin options can be programmed for input, output, or bi-directional operation. Each bi-directional I/O pin is associated with an I/O cell which features an input/feedback register, an input buffer, output/feedback register, three-state output buffer, an output enable register, and two 2-to-1 multiplexers. For input functions, I/O pins can provide combinatorial registered data or both options simultaneously to the logic array. For combinatorial input operation, data is routed from I/O pins through the input buffer to the array logic. For registered input operation, I/O pins drive the D input of input cell registers, allowing data to be captured with fast set-up times without consuming internal logic cell resources. For output functions, I/O pins can receive combinatorial or registered data from the logic array. For combinatorial output operation, data is routed from the logic array through a multiplexer to the I/O pin. For registered output operation, the array logic drives the D input of the output cell register which in turn drives the I/O pin through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be driven to the I/O pin. The three-state output buffer controls the flow of data from the array logic to the I/O pin and allows the I/O pin to act as an input and/or output. The buffer's output enable can be individually controlled by a logic cell array or any pin (through the regular routing resources), or bank-controlled through one of the global networks. The signal can also be either combinatorial or registered. This is identical to that of the flow for the output cell. For combinatorial control operation, data is routed from the logic array through a multiplexer to the three-state control. For registered control operation, the array logic drives the D input of the OE cell register which in turn drives the three-state control through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be driven to the three-state control. For output functions, I/O pins can be individually configured for active HIGH, active LOW, or open-drain inverting operation. In the active HIGH and active LOW modes, the pins of all devices are fully 3.3 V compliant.
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
When I/O pins are unused, the OE controls can be permanently disabled, allowing the output cell register to be used for registered feedback into the logic array. I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular routing resources, from one of the global networks, or from two input pins per bank of I/O's. The CLK and RESET signals share a common line, while the clock enables for each register can be independently controlled. Additionally, the output and enable registers will increase a device's register count. The addition of an output register will also decrease the TCO. Since the output register does not need to drive the routing, the length of the output path is also reduced. Extra registers add more inputs and outputs to the I/O structure. Extra routing resources are added to connect the I/O structure to the other parts of the device. I/O interface support is programmable on a per bank basis. There are 4 I/O banks per chip. Users can not mix a 2.5 volt I/O with 3.3 volt I/O on the same I/O bank. Figure 52 illustrates the multiple I/O bank configurations.
VCCIO 0
VREF 0
I/O Bank 0
I/O Bank 3
VCCIO 3
I/O Bank 1
I/O Bank 2 VREF 2 VCCIO 2
VCCIO 1
VREF 3
VREF 1
Figure 52: Multiple I/O Bank Configurations
Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and VREF supplies. A mixture of different I/O standards can be used on the device; however, there is a limitation as to which I/O standards can be supported within a given bank. Differential I/O can be shared with non differential I/O. There can only be one VREF and one VCCIO per bank.
Programmable Slew Rate
Each I/O has programmable slew rate capability. The rate is programmable to one of two slew rates: either fast or slow. The slower rate can be used to reduce ground bounce noise. The slow slew rate is 1 V/ns under typical conditions. The fast slew rate is 2.8 V/ns
Table 34: 3.3 V Slew Rate VCCIO = 3.3 V Rising Edge Falling Edge Fast Slew 2.8 V/nS 2.86 V/nS Slow Slew 1.0 V/vS 1.0 V/nS
(c) 2002 QuickLogic Corporation
Preliminary
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* * 43 * *
QL82SD Device Data Sheet Rev C
.
Table 35: 2.5 V Slew Rate VCCIO = 2.5 V Rising Edge Falling Edge Fast Slew 1.7 V/nS 1.9 V/nS Slow Slew 0.6 V/vS 0.6 V/nS
NOTE: Condition: 2.5 V, 25 C
Programmable Weak-Pull
Programmable weak pull-down resistors are available on each I/O. I/O Weak Pull-Down eliminates the need for an external pull-down resistor for used I/O. The spec for pull-down current is a maximum of 150 uA under a worst case condition. -148 uA @ 3.6 V, -55 C, - 69 uA@ 2.5 V, 25 C. Figure 53 illustrates the weak pull-down circuit.
I/O Register 1
PAD
Figure 53: I/O Weak Pull-Down Circuit
I/O Control and Local Hi-Drives
Each bank of I/Os has two input-only pins that can be programmed to drive the RST, CLK, and EN inputs of I/O's in that bank. These input-only pins also double up as high-drive inputs to a quadrant. Both as an I/O control or high-drive, these buffers can be driven by the internal logic. The I/O control network and local high-drive performance is indicated in
Table 36.
Table 36: I/O Control Network/ Local Hi-Drive Performance TT, 25C, 2.5V I/O (slow) I/O (fast) Skew From Pad 1.00 ns 0.63 ns 0.37 ns From Array 1.14 ns 0.78 ns 0.36 ns
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Programmable Logic Routing
The QL82SD device provides six types of routing resources (as in the QuickRAM devices): short (sometimes called segmented) wires, dual wires, quad wires, express wires, distributed networks, and defaults.
* Short wires span the length of one logic cell, always in the vertical direction. Dual wires
run horizontally and span the length of two logic cells. NOTE: Short and dual wires are predominantly used for local connections. They effectively traverse one or two logic cells that utilize an interconnect element to continue to the next cell or to change direction.
* Quad wires have passive link interconnect elements every fourth logic cell. As a result,
these wires are typically used to implement intermediate or medium length fan-out nets.
* Express lines run the length of the programmable logic uninterrupted. Each of these
lines has a higher capacitance than a quad, dual or short wire, but less capacitance than shorter wires connected to run the length of the device. The resistance will also be lower because the express wires don't require the use of "pass" links. Express wires provide higher performance for long routes or high fan-out nets.
* Distributed networks are described in the clock/control section. These wires span the
programmable logic, and are driven by "column clock" buffers. Each dedicated clock network pin buffer is hard wired to a set of column clock buffers. Five global networks "global buffers" can be connected through special purpose routing called "HSCK lines" to either a dedicated pin buffer, or any vertical routing wire crossing it.
Global POR (Power-On Reset)
The QuickSD device features a global power-on reset. This reset will be hardwired to all registers and will reset the registers upon power-up of the device. The circuitry used to support the global POR is similar to the power-up loading circuitry.
VCC
Power-on Reset
Q
0
Figure 54: Power-On Reset
Separate Power & Logic Cell Power
To decrease the logic cell area and to eliminate the need for disable transistors in the input stage of the logic cell, a separate power supply for the logic cells has been added to the QuickSD device. This supply will be grounded during programming and for various test modes.
(c) 2002 QuickLogic Corporation
Preliminary
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* * 45 * *
QL82SD Device Data Sheet Rev C
IEEE Standard 1149.1a
The QuickSD device supports IEEE standard 1149.1a. The following public instructions are supported: BYPASS, EXTEST, and SAMPLE/PRELOAD. Two additional modes RAMWT and RAMRD can be used to load the RAM.
TCK TMS TRSTB
Tap Controller State Machine (16 States)
Instruction Decode & Control Logic
Instruction Register
RDI
Mux Boundary-Scan Register (Data Register)
Mux
TDO
Bypass Register
Logic Cell Array
I/O Registers
User Defined Data Register
Figure 55: JTAG Block Diagram
JTAG BSDL Support
* BSDL-Boundary Scan Description Language * Machine-readable data for test equipment to generate testing vectors and software * BSDL files available for all device/ package combinations from QuickLogic * Extensive industry support available and ATG (Automatic Test-vector Generation)
Security Fuses
There are two security links, one to disable reading from the array and the other to disable JTAG.
8-bit Programming
The QuickSD device has 8-bit programming capability. The addition of four extra programming supplies is used in the reduction of programming time.
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Pin Type Description
General Pins
Table 37: General Pin Descriptions Type IN OUT T/S Description Input. A standard input-only signal Totem pole output. A standard active output driver Tri-state. A bi-directional, tri-state input/output pin Table 38: General Pin/Bus Descriptions Pin/Bus Name VCC VCCIO Type IN IN Function Supply pin. Tie to 2.5 V supply. Supply pin for I/O. Set to 2.5 V for 2.5 V I/O, 3.3 V for 3.3 V compliant I/O, or refer to the I/O Standards table. Differential I/O Reference Voltage, refer to Differential Voltage Table. Connect to GND when using TTL, PCI or LVCMOS LVDS Receiver VCC Supply. Connect to 3.3 V PLL VCC Supply. Connect to 2.5 V Low Skew I/O Control Pins. Tie to GND if unused Tie to GND Programmable Global Clock Pin or Programmable PLL Input. Tie to VCC or GND if unused Dedicated Global Clock Pin or Programmable PLL Input.
INREF VCCREC VCCPLL IOCTRL GNDPLL CLK/PLLIN CLK/DEDCLK/PLLIN PLLOUT PLLRST GND T/GND I/O CLK TDI TDO TCK TMS TRSTB NC
IN IN IN IN IN IN IN
OUT Programmable PLL Output IN IN IN Programmable PLL Reset. Tie to VCC if the PLL is unused. Ground pin. Tie to GND on the PCB. Thermal Ground. Used to dissipate heat from the device. Tie to GND on the PCB.
T/S Programmable Input/Output/Tri-State/Bi-directional Pin. IN IN Programmable Global Clock Pin. Tie to VCC or GND if unused. JTAG Data In. Tie to VCC if unused.
OUT JTAG Data Out. Leave unconnected if unused. IN IN IN OUT JTAG Clock. Tie to GND if unused. JTAG Test Mode Select. Tie to VCC if unused. JTAG Reset. Tie to GND if unused. Must be isolated and floating at all times
(c) 2002 QuickLogic Corporation
Preliminary
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* * 47 * *
QL82SD Device Data Sheet Rev C
LVDS SERDES External Signals
Table 39: LVDS SERDES External Signals Signal Name CH0P, CH0N CH1P, CH1N CH2P, CH2N CH3P, CH3N CH4P, CH4N CH5P, CH5N CH6P, CH6N CH7P, CH7N CLKAP, CLKAN CLKBP, CLKBN Description LVDS signal pair for data channel 0 LVDS signal pair for data channel 1 LVDS signal pair for data channel 2 LVDS signal pair for data channel 3 LVDS signal pair for data channel 4 LVDS signal pair for data channel 5 LVDS signal pair for data channel 6 LVDS signal pair for data channel 7 LVDS signal pair for channel clock A LVDS signal pair for channel clock B
LVDS SERDES Internal Signals (Data Channels 0 to 7)
Table 40: LVDS SERDES Internal Signals (Data Channels 0 to 7) Signal Name Ch0_rst Ch0_oe Ch0_en Channel 0 Reset Signal Channel 0 Output Enable (1=transmit, 0=receive) Channel 0 Enable (reduces power when set to 0) Description
Ch0_mode[3:0] Channel 0 MODE pins. See the SERDES Data Channel Functional Description Ch0_txd[9:0] Ch0_txclk Ch0_sync Ch0_rxd[9:0] Ch0_rxclk Ch0_lock Ch0_pre_emp Channel 0 Parallel Transmit Data Bus Channel 0 Transmit/Reference Clock Channel 0 Sync Control. When low, a sync pattern is generated on the CH0_DATA pins to provide a high-speed lock mechanism when using the embedded clock mode. When high, it will send the data in ChX_txd. Channel 0 Parallel Receive Data Bus Channel 0 Receive Clock Channel 0 Lock indicator, to indicate when the SERDES is locked to the serial bitstream, when using the embedded clock mode. Channel 0 pre-emphasis signal. When high, LVDS transmitter boosts dynamic current during signal transitions.
NOTE: All Ch0 signals above repeat for Ch1-Ch7. The eight SERDES data channels 0 through 7 are identical.
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
LVDS SERDES Internal Signals (Channel Clocks A and B)
Table 41: LVDS SERDES Internal Signals (Channel Clocks A and B) Signal Name ClkA_rst ClkA_oe ClkA_en ClkA_mode[1:0] ClkA_txclk ClkA_rxclk Channel Clock A Reset Signal Channel Clock A Output Enable (1 =transmit, 0=receive) Channel Clock A Enable (reduces power when set to 0) Channel Clock A MODE pins. See the SERDES Channel Clock Functional Description Channel Clock A Parallel Transmit Clock Channel Clock A Parallel Receive Clock Description
NOTE: All ClkA signals above repeat for ClkB. SERDES channel clocks A and B are identical.
208 PQFP Pinout Diagram
Pin #1 Pin #157
QuickSD QL82SD-6PQ208C
Pin #53
Figure 56: QL82SD - 208PQFP Pinout Diagram
Pin #105
(c) 2002 QuickLogic Corporation
Preliminary
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* * 49 * *
QL82SD Device Data Sheet Rev C
208 PQFP Pinout Table
Table 42: 208 PQFP Pinout Table
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Function
VCCPLL GNDPLL VCC GND Ch0N Ch0P GND VCC GND VCCREC VCCPLL GNDPLL VCC GND Ch1N Ch1P VCC GND VCCREC GND VCC GND GND ClkAN ClkAP VCC ClkBN ClkBP GND VCCREC VCC GND GND VCCPLL GNDPLL Ch6N Ch6P GND VCC GND VCCREC VCC
Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Function
VCCPLL GNDPLL GND Ch7N Ch7P GND VCC GND VCCREC VCC GND VCC GND VCC TRSTB CLK(2) CLK(3)PLLI N(1) CLK(4)DED CLK, PLLIN(0) IO(A) IO(A) IO(A) IO(A) VCC GND VCCIO(A) IO(A) IO(A) VCC IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) VCC IO(A) GND IO(A) IOCTRL(A)
Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
Function
INREF(A) IOCTRL(A) VCC IO(A) IO(A) VCCIO(A) IO(A) IO(A) IO(A) IO(A) GND IO(A) IO(A) IO(B) IO(B) IO(B) IO(B) PLLOUT(0) GNDPLL(1) GND PLLRST(1) VCCPLL(1) VCCIO(B) IO(B) GND IO(B) IO(B) VCC IO(B) IO(B) IO(B) IO(B) IOCTRL(B) INREF(B) IOCTRL(B) GND IO(B) VCCIO(B) IO(B) VCC IO(B) VCC
Pin 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Function
GND CLK(5) CLK(6) CLK(7) CLK(8) TMS GND IO(C) IO(C) IO(C) IO(C) VCC IO(C) VCCIO(C) IO(C) VCC IO(C) IOCTRL(C) INREF(C) GND IOCTRL(C) IO(C) IO(C) IO(C) VCC IO(C) GND VCCIO(C) PLLOUT(1) GNDPLL(0 ) GND PLLRST(0) VCCPLL(0) IO(C) IO(C) IO(C) IO(D) IO(D) IO(D) IO(D) GND IO(D)
Pin 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Function
IO(D) VCCIO(D) VCC IO(D) IO(D) IO(D) IOCTRL(D) INREF(D) IOCTRL(D) IO(D) IO(D) IO(D) IO(D) VCCIO(D) IO(D) IO(D) VCC GND IO(D) IO(D) IO(D) IO(D) VCC VCCIO(D) IO(D) IO(D) GND IO(D) IO(D) VCC CLK(0) CLK(1) TCK VCC TDI GND VCC GND TDO GND
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
280 FPBGA Pinout Diagram
QUICKSD QL82SD-6PT280C
Figure 57: QL82SD - 280 FPBGA Top View
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN A1 CORNER
A B C D E F G H J K L M N P R T U V W
Figure 58: QL82SD - 280 FPBGA Bottom View
(c) 2002 QuickLogic Corporation
Preliminary
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* * 51 * *
QL82SD Device Data Sheet Rev C
280 FPBGA Pinout Table
Table 43: 280 FPBGA Pinout Table
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 Function
PLLOUT(1) IO(C) IO(C) IO(C) INREF(C) IOCTRL(C) IO(C) IO(C) IO(C) CLK(7) IO(B) IO(B) IOCTRL(B) IOCTRL(B) IO(B) IO(B) IO(B) IO(B) IO(B) PLLRST(0) IO(C) IO(C) IO(C) IOCTRL(C) IO(C) IO(C) IO(C) TMS CLK(5) IO(B) IO(B) IO(B) INREF(B) IO(B) IO(B) IO(B) PLLRST(1) GND IO(C) GND GNDPLL(0) IO(C) VCCIO(C) IO(C) IO(C) IO(C) VCCIO(C)
Pin C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18
Function
CLK(8) VCCIO(B) IO(B) IO(B) IO(B) VCCIO(B) IO(B) VCCPLL(1) GNDPLL(1) PLLOUT(0) IO(C) IO(C) VCCPLL(0) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) CLK(6) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(C) IO(C) VCCIO(D) IO(D) GND VCC VCC VCC VCC GND GND VCC VCC GND GND IO(A) VCCIO(A) IO(B)
Pin E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J15 J16 J17 J18 J19 K1 K2 K3 K4 K5 K15
Function
IO(B) IO(D) IO(D) IO(D) IO(D) GND VCC IO(A) IO(A) IO(A) IO(B) IO(D) IO(D) IO(D) IO(D) VCC VCC IO(A) IO(A) IO(A) IO(A) IO(D) IO(D) IO(D) IO(D) VCC VCC IO(A) IO(A) IO(A) IO(A) IOCTRL(D) INREF(D) VCCIO(D) IO(D) GND VCC IO(A) VCCIO(A) IO(A) IOCTRL(A) IO(D) IOCTRL(D) IO(D) IO(D) GND GND
Pin K16 K17 K18 K19 L1 L2 L3 L4 L5 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R3
Function
IO(A) IO(A) INREF(A) IOCTRL(A) IO(D) IO(D) IO(D) IO(D) VCC GND IO(A) IO(A) IO(A) IO(A) IO(D) IO(D) VCCIO(D) IO(D) VCC VCC IO(A) VCCIO(A) IO(A) IO(A) IO(D) CLK(0) IO(D) IO(D) VCC VCC IO(A) IO(A) IO(A) IO(A) IO(D) TCK IO(D) IO(D) VCC GND CLK(4) DEDCLK, PLLIN(0) CLK(3) PLLIN(1) IO(A) IO(A) IO(D) TDI CLK(1)
Pin R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12
Function
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC CLK(2) TRSTB IO(A) IO(A) IO(D) GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND IO(A) IO(A) TDO VCCPLL GNDPLL VCCPLL GNDPLL VCCPLL GNDPLL VCCPLL GNDPLL NC VCCPLL GNDPLL
Pin U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19
Function
VCCPLL GNDPLL VCCPLL GNDPLL VCCPLL GNDPLL VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC Ch7P Ch0N Ch0P Ch1N Ch1P Ch2N Ch2P Ch3N Ch3P ClkAN ClkAP ClkBN ClkBP Ch4N Ch4P Ch5N Ch5P Ch6N Ch6P Ch7N
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Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
484 PBGA Pinout Diagram
QUICKSD QL82SD-6PS484C
Figure 59: QL82SD - 484PBGA Top View
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN A1 CORNER A B C D E F G H J K L M N P R T U V W Y AA AB
Figure 60: QL82SD - 484PBGA Bottom View
(c) 2002 QuickLogic Corporation
Preliminary
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* * 53 * *
QL82SD Device Data Sheet Rev C
484 PBGA Pinout Table
Table 44: 484 PBGA Pinout Table
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 Function
GND NC I/O I/O I/O I/O I/O I/O I/O I/O I/O IOCTRL I/O I/O I/O I/O I/O I/O I/O GND PLLOUT<1> I/O CH0N GND TDO GND I/O I/O TDI I/O I/O I/O I/O I/O IOCTRL I/O I/O I/O I/O I/O PLLRST<0> I/O I/O I/O CH0P VCCREC GND GND NC I/O I/O I/O
Pin D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2
Function
I/O I/O VCCPLL<0> I/O I/O I/O CH1P VCCREC VCCREC GNDPLL GND NC NC CLK<1> I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CH2N VCCREC VCCREC VCCPLL GND VCC VCCIO NC VCCIO I/O VCCIO VCCIO I/O VCCIO I/O VCCIO I/O I/O I/O IOCTRL I/O IOCTRL CH2P VCCREC
Pin H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18
Function
VCC GND VCC VCC GND NC NC I/O I/O I/O I/O I/O CH3P VCCREC VCCREC GNDPLL GND VCC VCC VCC GND VCC VCC GND VCC GND VCC NC VCCIO I/O I/O I/O I/O I/O CLKAN VCCREC VCCREC VCCPLL GND VCC VCC VCC VCC GND GND GND GND VCC VCC NC I/O I/O
Pin M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12
Function
GND VCC VCC VCC VCC GND GND GND GND GND GND GND I/O I/O I/O CLK<7> CLK<5>/PLL IN<3> TMS CLKBP VCCREC VCCREC GNDPLL GND VCC VCC VCC VCC GND GND GND GND VCC VCC I/O VCCIO I/O I/O I/O I/O I/O CH4N VCCREC VCCREC VCCPLL GND VCC VCC VCC GND VCC GND VCC
Pin R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6
Function
I/O I/O CH5N VCCREC VCCREC VCCPLL GND VCC GND NC NC NC GND NC NC NC NC GND I/O I/O I/O I/O IOCTRL I/O CH5P VCCREC VCCREC GNDPLL GND VCC VCCIO I/O VCCIO NC VCCIO VCCIO NC VCCIO NC VCCIO VCCIO I/O I/O
Pin W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA15 AA16 AA17 AA18 AA19 AA21 AA22
Function
I/O I/O NC I/O I/O I/O I/O I/O CH7N VCCREC GND NC I/O I/O I/O I/O I/O I/O I/O IOCTRL IOCTRL I/O I/O I/O I/O I/O PLLOUT<0> PLLRST<1> I/O I/O CH7P GND GND I/O I/O I/O I/O I/O I/O I/O I/O INREF I/O I/O I/O I/O I/O I/O I/O
IOCTRL AA14 I/O INREF CH6N VCCREC VCCREC VCCPLL GND NC
AA20 GNDPLL<1>
I/O I/O
(Sheet 1 of 2)
* * 54 * www.quicklogic.com * * *
Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Table 44: 484 PBGA Pinout Table
Pin C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 Function
I/O I/O I/O INREF I/O I/O I/O I/O I/O I/O I/O GNDPLL <0> I/O I/O CH1N VCCREC VCCREC VCCPLL NC NC VCC TCK I/O I/O I/O I/O I/O I/O I/O I/O
Pin G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10
Function
VCCREC GNDPLL GND VCC GND NC CLK<0> NC NC GND NC NC I/O GND VCCIO I/O I/O I/O INREF I/O CH3N VCCREC VCCREC VCCPLL GND VCC VCC GND VCC VCC
Pin K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4
Function
I/O I/O I/O I/O CLKAP VCCREC VCCREC GNDPLL GND VCC GND GND GND GND GND GND GND VCC VCC CLK<6> VCCIO I/O CLK<8> I/O I/O I/O CLKBN VCCREC VCCREC VCCPLL
Pin P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20
Function
VCC GND VCC I/O I/O I/O I/O I/O I/O I/O CH4P VCCREC VCCREC GNDPLL GND VCC VCC GND VCC VCC GND VCC VCC VCC GND NC VCCIO I/O I/O I/O
Pin V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14
Function
CLK<2>/PLL IN<2> NC I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O CH6P VCCREC VCCREC GNDPLL NC TRSTB CLK<3>/PLL IN<1> CLK<4> DEDCLK/PL LIN<0> I/O I/O I/O I/O I/O I/O
Pin AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB22
Function
GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
AB21 VCCPLL<1>
I/O
(Sheet 2 of 2)
(c) 2002 QuickLogic Corporation
Preliminary
www.quicklogic.com * *
* * 55 * *
QL82SD Device Data Sheet Rev C
516 PBGA Pinout Diagram
QUICKSD QL82SD-6PB516C
Figure 61: QL82SD - 516PBGA Top View
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN A1 CORNER
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
Figure 62: QL82SD - 516PBGA Bottom View
* * 56 * www.quicklogic.com * * *
Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
516 PBGA Pinout Table
Table 45: 516 PBGA Pinout Table
Pin A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C01 C02 Function
NC IO(C) IO(C) IOCTRL(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) TMS CLK(8) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IOCTRL(B) IO(B) IO(B) IO(B) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) CLK(7) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) NC INREF(B) IO(B) IO(B) IO(B) IO(B) IO(C) IO(C)
Pin D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F01 F02 F03 F04 F05 F06 F07 F08 F09 F10
Function
IO(C) IO(C) IO(C) IO(C) IO(C) CLK(5) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) INREF(C) VCC IO(C) IO(C) IO(C) VCC IO(C) IO(B) IO(B) VCC IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) VCCPLL(0) GNDPLL(0) IO(C) IO(C) IO(C) GND VCCIO(C) VCC VCCIO(C) GND
Pin H05 H06 H21 H22 H23 H24 H25 H26 J01 J02 J03 J04 J05 J06 J21 J22 J23 J24 J25 J26 K01 K02 K03 K04 K05 K06 K21 K22 K23 K24 K25 K26 L01 L02 L03 L04 L05 L06 L11 L12 L13 L14 L15 L16 L21 L22 L23 L24 L25 L26 M01 M02 M03 M04
Function
IO(C) VCC VCC VCC PLLRST(1) GND IO(B) IO(B) IO(D) IO(D) IO(C) IO(C) IO(C) VCCIO(D) VCCIO(A) PLLOUT(0) IO(B) IO(B) IO(B) IO(A) IO(D) IO(D) IO(D) IO(D) IO(C) GND GND IO(B) IO(B) IO(B) IO(A) IO(A) IO(D) IO(D) IO(D) IO(D) VCC VCC GND GND GND GND GND GND VCC IO(A) IO(A) IO(A) IO(A) IO(A) IO(D) NC IO(D) IO(D)
Pin P01 P02 P03 P04 P05 P06 P11 P12 P13 P14 P15 P16 P21 P22 P23 P24 P25 P26 R01 R02 R03 R04 R05 R06 R11 R12 R13 R14 R15 R16 R21 R22 R23 R24 R25 R26 T01 T02 T03 T04 T05 T06 T11 T12 T13 T14 T15 T16 T21 T22 T23 T24 T25 T26
Function
IO(D) IOCTRL(D) INREF(D) IOCTRL(D) IO(D) VCCIO(D) GND GND GND GND GND GND VCCIO(A) IOCTRL(A) IO(A) IOCTRL(A) IO(A) NC IO(D) IO(D) IO(D) IO(D) VCC VCC GND GND GND GND GND GND VCC IO(A) IO(A) IO(A) IO(A) INREF(A) IO(D) IO(D) IO(D) IO(D) IO(D) VCC GND GND GND GND GND GND VCC VCC IO(A) IO(A) IO(A) IO(A)
Pin W23 W24 W25 W26 Y01 Y02 Y03 Y04 Y05 Y06 Y21 Y22 Y23 Y24 Y25 Y26 AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12
Function
IO(A) IO(A) IO(A) IO(A) IO(D) IO(D) IO(D) IO(D) CLK(1) VCCIO(D) VCCIO(A) CLK(4)DED CLK, PLLIN(0) IO(A) IO(A) IO(A) IO(A) IO(D) IO(D) IO(D) CLK(0) GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC GND VCC IO(A) IO(A) IO(A) IO(A) IO(D) IO(D) NC VCC GND GND GND GND GND GND GND GND
Pin AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20
Function
GNDPLL VCCPLL GNDPLL GND NC GND IO(A) IO(A) IO(D) TDI GND VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC GND CLK(2) IO(A) TCK TDO GND VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC VCCREC
(Sheet 1 of 2) www.quicklogic.com * *
* * 57 * *
(c) 2002 QuickLogic Corporation
Preliminary
QL82SD Device Data Sheet Rev C
Table 45: 516 PBGA Pinout Table
Pin C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D01 D02 D03 D04 D05 D06 D07 D08 Function
IO(C) IO(C) IOCTRL(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) CLK(6) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IOCTRL(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C)
Pin F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G01 G02 G03 G04 G05 G06 G21 G22 G23 G24 G25 G26 H01 H02 H03 H04
Function
VCC VCCIO(C) GND VCCIO(B) VCC VCC GND VCCIO(B) VCC VCCIO(B) GND IO(B) IO(B) IO(B) IO(B) VCCPLL(1) IO(C) GND PLLOUT(1) IO(C) IO(C) VCCIO(D) VCCIO(A) IO(B) IO(B) IO(B) IO(B) GNDPLL(1) IO(C) IO(C) IO(C) PLLRST(0)
Pin M05 M06 M11 M12 M13 M14 M15 M16 M21 M22 M23 M24 M25 M26 N01 N02 N03 N04 N05 N06 N11 N12 N13 N14 N15 N16 N21 N22 N23 N24 N25 N26
Function
IO(D) VCCIO(D) GND GND GND GND GND GND VCCIO(A) VCC IO(A) IO(A) IO(A) IO(A) IO(D) IO(D) IO(D) IO(D) IO(D) GND GND GND GND GND GND GND GND IO(A) IO(A) IO(A) IO(A) IO(A)
Pin U01 U02 U03 U04 U05 U06 U21 U22 U23 U24 U25 U26 V01 V02 V03 V04 V05 V06 V21 V22 V23 V24 V25 V26 W01 W02 W03 W04 W05 W06 W21 W22
Function
IO(D) IO(D) IO(D) IO(D) IO(D) GND GND IO(A) IO(A) IO(A) IO(A) IO(A) NC IO(D) IO(D) IO(D) IO(D) VCCIO(D) VCCIO(A) IO(A) IO(A) NC IO(A) IO(A) IO(D) IO(D) IO(D) NC VCC VCC VCC IO(A)
Pin AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18
Function
GND GND GND GND GND GND GND GND GND GND TRSTB IO(A) IO(A) NC IO(D) IO(D) NC GND GND VCCPLL GNDPLL VCCPLL GNDPLL VCCPLL GNDPLL VCCPLL GNDPLL VCCPLL GNDPLL VCCPLL GNDPLL VCCPLL
Pin AE21 AE22 AE23 AE24 AE25 AE26 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26
Function
VCCREC VCCREC VCCREC GND GND CLK(3)PLLI N(1) NC NC GND Ch0N Ch0P Ch1N Ch1P Ch2N Ch2P Ch3N Ch3P ClkAN ClkAP ClkBN ClkBP Ch4N Ch4P Ch5N Ch5P Ch6N Ch6P Ch7N Ch7P NC NC NC
(Sheet 2 of 2)
* * 58 * www.quicklogic.com * * *
Preliminary
(c) 2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Contact Information
Telephone: 408 990 4000 (US) 416 497 8884 (Canada) 44 1932 57 9011 (Europe) 49 89 930 86 170 (Germany) 852 8106 9091 (Asia) 81 45 470 5525 (Japan) E-mail: Support: Web site: info@quicklogic.com support@quicklogic.com http://www.quicklogic.com/
Revision History
Table 46: Revision History Revision Rev. A - Preliminary Rev. B - Preliminary Rev. C - Preliminary Date Sept. 2001 Dec. 2001 June 2002 Originator and Comments First Release - Paul Micallef and John Kim Changes to diagrams and data - Paul Micallef and John Kim Updated performance figures - Paul Micallef and John Kim
Copyright Information
Copyright (c) 2002 QuickLogic Corporation. All Rights Reserved. The information contained in this manual, and the accompanying software programs are protected by copyright-all rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to make periodic modifications of this product without obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited.
QuickLogic , pASIC , and ViaLink and QuickWorks are registered trademarks of QuickLogic Corporation.
Verilog
is a registered trademark of Cadence Design Systems, Inc.
(c) 2002 QuickLogic Corporation
Preliminary
www.quicklogic.com * *
* * 59 * *
QL82SD Device Data Sheet Rev C
* * 60 * www.quicklogic.com * * *
Preliminary
(c) 2002 QuickLogic Corporation
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